In modern electronic devices clocks or timers are used to accomplish various tasks. In modern data networks for example clocks or timers are needed for data shaping. Data shaping is required to smooth traffic burstiness to control and limit data packet queues at the receiving units and to enforce contract between service providers and clients.
In traffic shaping applications the incoming traffic is measured, and upon exceeding a certain limit defined for the data traffic, the incoming traffic is detained or delayed to maintain a stable data rate with minimum burstiness. Such a traffic shaper manages the delays of the data packets using timers for timing the delay of each single data packet or for timing delays in a data packet flow queue. When a timer signals that a delay has expired, the corresponding traffic is transmitted from the queue of delayed packets.
Traffic shapers for very high bandwidth applications delay millions of data packets or flow queues at any given time.
Managing a low number of delays can be realised using hardware timers for all the delayed packets or flow queues. But for millions of delays the number of counters, and thus the amount of integrated circuitry, like for example flip flops, would increase dramatically. This would increase the energy consumption and the cost of the device to levels which render such a traffic shaper uneconomical.
Therefore, for a large number of delays methods of timing those delays have been developed, that include a processor and data memory for storing the delays. In such a traffic shaper a delay value is stored in a memory, and that delay value is constantly decremented until it reaches zero. If a delay value reaches zero, that delay expires and the data packet is transmitted or the flow queue is allowed to send traffic. In such a traffic shaper for every decrement of a delay value, a read and write access to the memory is necessary, followed by a compare to zero operation. If the range for the delay values is 0 to 1000, in a worst case scenario there would be 1000 read and write accesses to memory per each delay. This would cause performance bottlenecks when used with a great number of data packets or flow queues.
Consequently methods have been developed to reduce the amount of computation necessary for managing delays. One method comprises counting the single digits of a delay value with their corresponding rate. For example a delay of 987 would be counted as 9 hundreds-steps, 8 tens-steps and 7 ones-steps. Thus the amount of computation needed is reduced to the sum of the digits of the delay value. But depending on the amount of timers and the delay value range with millions of delays, the processing could still amount to such extent high value that performance issues could arise.